In order to electrically connect a semiconductor device to external devices, a probe is pressed against a pad provided in the semiconductor device upon an electrical test; or wire bonding is performed, or bumps are formed on the pad during assembly. For example, when pressing the probe against the pad upon the electrical test, stress is downwardly applied from an upper surface of the pad in the vertical direction. In such a state, it is required to break through an oxide film formed on a surface of the pad, and therefore stress is concentrated at a tip end of the probe. In addition, during the assembly by wire bonding etc., stress is similarly applied.
When such stress is excessively applied, cracks are caused in an insulating film supporting interconnects, resulting in current leakage. In addition, it also causes property variation of elements such as transistors.
Thus, an arrangement of the elements such as transistors and the interconnects below the pad has been avoided in order to reduce an influence of the stress caused upon the electrical test and during the assembly. However, a higher priority has been recently assigned to cost reduction by reducing a chip size, and the elements and the interconnects tend to be arranged below the pad.
For example, Japanese Patent Publication No. 2007-67332 (hereinafter referred to as “Patent Document 1”) describes a way to solve the problem due to the stress caused in the foregoing case. In Patent Document 1, a structure is employed, in which a plurality of interconnect layers are arranged below a pad. Further, as illustrated in FIG. 7, interconnects 112 arranged right below a pad 101 covers equal to or greater than 30% of the pad. This can reduce stress to be applied to the interconnect layers.